Digital voltage gain amplifier for zero if architecture

ABSTRACT

The invention is directed toward a digital VGA that is implemented in the logarithmic domain. The digital VGA exploits logarithmic properties to replace a complex multiplier of a conventional digital VGA with a simple and inexpensive adder. Moreover, additional techniques are described to significantly reduce the size of one or more lookup tables (LUTs) implemented within the digital VGA. In this manner, the invention can realize a simple, low cost digital VGA.

[0001] This application is a continuation of U.S. patent applicationSer. No. 09/954,589, filed Sep. 14, 2001., which claims priority fromU.S. Provisional Application Serial No. 60/305,968, entitled “DIGITALVOLTAGE GAIN AMPLIFIER IMPLEMENTATION IN LOGARITHMIC DOMAIN IN THE ZEROIF ARCHITECTURE,” filed Jul. 16, 2001, the content of which isincorporated herein by reference in its entirety. Co-pending andcommonly assigned U.S. application Ser. No. 09/954,760, entitled“LOGARITHMIC LOOKUP TABLES” filed the same day as this application, andbearing Attorney Docket No. 010420 is also hereby incorporated herein byreference in its entirety.

FIELD

[0002] The invention relates generally to wireless communication systemsand, more particularly, to voltage gain amplifiers within wirelesscommunication systems.

BACKGROUND

[0003] One common technique used in wireless communication is codedivision multiple access (CDMA) signal modulation in which multiplecommunications are simultaneously conducted over a radio-frequency (RF)spectrum. Some example wireless communication devices that haveincorporated CDMA technology include cellular radiotelephones, PCMCIAcards incorporated within computers, personal digital assistants (PDAs)equipped with wireless communication capabilities, and the like.

[0004] A conventional architecture for a CDMA receiver includes aradio-frequency (RF) section and an infrared (IF) section. Inparticular, the received RF signals are typically filtered in the RFsection, converted from RF signals to IF signals for further filteringand scaling by a voltage gain amplifier (VGA) in the IF section, andfinally converted to baseband signals. The baseband signals aretypically passed through an analog-to-digital (A/D) converter to producedigital samples which can be sent to a digital signal processor fortracking and demodulation.

[0005] The Zero infrared frequency (Zero IF) architecture is a morerecent architecture used in CDMA wireless communication devices. Unlikeother conventional architectures, the Zero IF architecture convertsincoming RF signals directly into baseband signals without firstconverting the RF signals to IF signals. In particular, the Zero IFarchitecture makes use of a digital VGA that scales the digital samplesproduced by the A/D converter. In this manner, the Zero IF architectureeliminates the need for various IF components, including an IF mixer, anIF VGA and IF filters.

[0006] In the heterodyne architecture with an IF section, the IF-VGAcontrolled by an automatic gain control unit (AGC) is responsible foreither expanding or compressing the signal such that it fits in therelatively narrow dynamic range of the A/D converter. The A/D convertercan then produce small bit-width (typically 4 bits) numbers so that restof the hardware that performs signal processing can be simplified. Inthe Zero-IF architecture however, due to the absence of the IF VGA, theA/D converter is typically designed to have much larger dynamic rangeresulting in large bit-width numbers at the output.

[0007] Although the Zero IF architecture eliminates the need for IFcomponents, the architecture may require more complicated basebandcomponents, primarily due to the relatively large digital signals(typically 18 bits) generated by the A/D converter. Consequently, adigital VGA is implemented at baseband to scale the large bit-widthsignals from the A/D converter. The Zero IF architecture may implement arelatively wide multiplier (typically an 18-bit by 18-bit multiplier) toscale the large digital signals. In addition, the digital VGA typicallyincludes a relatively large lookup table (LUT) (often exceeding akilobyte or more) to convert values received from the AGC unit fromlogarithmic units in decibels (dB) to linear values for controlling thegain of the digital VGA. In operation, for example, the digital VGAmultiplies the linear digital signals received from the A/D converter bya linear gain value obtained from the LUT. For these reasons, wirelesscommunication devices incorporating the Zero IF architecture may havesignificant cost even though the IF components have been eliminated.

SUMMARY

[0008] In general, the invention is directed toward a digital voltagegain amplifier (digital VGA) that operates within the logarithmicdomain. In particular, the digital VGA scales digital input values inaccordance with logarithmic gain values. Among other advantages,properties of the logarithmic domain are exploited to replace thecomplex multiplier of a conventional VGA with a simple and relativelyinexpensive adder. Additional techniques are described to significantlyreduce the size of one or more LUTs implemented within the digital VGA.In this manner, the invention can realize a much more simple, lower costdesign of a digital VGA.

[0009] Although not so limited, the digital VGA is particularly usefulwithin CDMA wireless communication devices that incorporate the Zero IFarchitecture. The invention greatly simplifies the manner in whichrelative large digital signals can be processed, reducing thecomplexity, memory space and cost of the wireless communication device.Other non-CDMA Zero-IF architectures can also benefit from theinvention.

[0010] In one embodiment, the invention comprises a digital voltage gainamplifier. The amplifier may include a logarithmic conversion unit thatconverts a baseband signal from a linear domain to a logarithmic domainand an adder that sums the converted baseband signal with a gain signalto produce a scaled baseband signal. In addition, the amplifier mayinclude an exponential conversion unit that converts the scaled basebandsignal from the logarithmic domain to the linear domain.

[0011] In another embodiment, the invention comprises a wirelesscommunication device. For example, the wireless communication device mayinclude an antenna that receives an RF signal and an RF mixer thatgenerates a baseband signal from the RF signal. In addition, thewireless communication device may include the voltage gain amplifierdescribed above to scale the baseband signal. The wireless communicationdevice may also include digital signal processor that processes at leastpart of the scaled baseband signal in the linear domain.

[0012] In still other embodiments, the invention may comprise one ormore methods. For example, a method may include converting a basebandsignal from a linear domain to a logarithmic domain, and adding theconverted baseband signal to a gain to generate a scaled basebandsignal. The method may also include converting the scaled basebandsignal from the logarithmic domain to the linear domain. The conversionsmay utilize lookup tables. Additional techniques can be used to reducethe size of the lookup tables and thus reduce memory requirements.

[0013] In yet another embodiment, the invention can avoid the use of amultiplier in a digital VGA. For example, a multiplication functionfollowed by optional truncation can be performed by first converting thetwo inputs to be multiplied into the logarithmic domain. The inputsignals can then be added or subtracted in the logarithmic domain beforebeing converted back to a linear domain with just enough bits to mimicthe original truncation operation.

[0014] The invention can provide a number of advantages. For example,the invention can provide a more simple, lower cost design of a digitalVGA for use in Zero IF architecture. In particular, the invention mayeliminate the need for a complex and relatively expensive multiplier,which can be replaced with a much more simple and inexpensive adder. Inaddition, because the inventive amplifier operates in the logarithmicdomain, the need to convert the gain values to a linear domain can besimplified, or avoided altogether. In one embodiment, for example, adigital VGA scales digital input values within the logarithmic domainusing logarithmic gain values in units of decibels. In that case, thegain values can be provided to the adder without any conditioning orconversion.

[0015] The invention may also significantly reduce memory requirementsin a digital VGA by using techniques to reduce the size of one or moreLUTs implemented in the digital VGA. In particular, an exponentialconversion unit may saturate a baseband signal in the logarithmic domainprior to converting the baseband signal back into a linear domain. Thesaturation prior to lookup can reduce the size (i.e., width) of theindividual entries in the LUT, thus reducing the amount of memoryrequired for the LUT. In addition, a logarithmic conversion unit mayutilize different LUTs for the exponent and the mantissa of a floatingpoint number, as described in detail below, which can drastically reducememory requirements. In particular, only a portion of the mantissavalues may be stored in the mantissa LUT, and the additional values canbe generated or approximated as needed.

[0016] Additional details of these and other embodiments are set forthin the accompanying drawings and the description below. Other features,objects and advantages will become apparent from the description anddrawings, and from the claims.

BRIEF DESCRIPTION OF DRAWINGS

[0017]FIG. 1 is a block diagram illustrating a wireless communicationdevice according to the invention.

[0018]FIG. 2 is a flow diagram according to an embodiment of theinvention.

[0019]FIG. 3 is a block diagram illustrating an embodiment of digitalVGA according to the invention.

[0020]FIG. 4 is a block diagram, illustrating in greater detail, oneembodiment of digital VGA.

[0021]FIGS. 5A-5C illustrate three different exemplary embodiments of anexponential conversion unit according to the invention.

[0022]FIG. 6 is a block diagram, illustrating in greater detail, oneimplementation of a logarithmic conversion unit.

[0023]FIGS. 7A and 7B are a series of two graphs that further illustratethe concept behind the embodiment of logarithmic conversion unitillustrated in FIG. 6.

[0024]FIGS. 8 and 9 are flow diagrams according to the invention.

DETAILED DESCRIPTION

[0025]FIG. 1 is a block diagram of an exemplary wireless communicationdevice (WCD) 100 according to the invention. Although not so limited,various embodiments of the invention are described in reference to areceiver of wireless communication device that implements the Zero IFarchitecture, as illustrated in FIG. 1. In that case, WCD 100 convertsincoming RF signals directly into baseband signals and, specifically,does not first convert the RF signals to IF signals.

[0026] WCD 100 includes antenna 104 that receives incoming RF signals.For example, the incoming RF signals may comprise code division multipleaccess (CDMA) modulated signals sent from a CDMA base station. An RFsignal received by antenna 104 can be passed through low-noise amplifier(LNA) 108 before being mixed down to baseband by RF mixer 112. Forexample, RF mixer 112 may receive carrier waveforms produced byfrequency synthesizer 116 that utilize a local clock of WCD 100 as atiming reference. The local clock, for instance, may comprise a voltagecontrolled oscillator 120, such as a voltage controlled temperaturecompensated crystal oscillator (VCTCXO). As desired, WCD 100 may alsoinclude additional components (not shown).

[0027] RF mixer 112 produces baseband signal 113, which can be filtered,e.g., by filter 124, and sampled by analog to digital (A/D) converter128 to produce corresponding digital values of the signal, e.g., digitalbaseband signal 129. Digital VGA 132 scales digital baseband signal 129,either by amplifying or attenuating the digital values according tologarithmic gain value 135 received from automatic gain control unit(AGC) 134.

[0028] After scaling by digital VGA 132, the scaled digital basebandsignal is provided to rake receivers 136, which separate and tracksignals received from different sources, e.g., different base stations.For example, rake receivers 136 may include a number of “fingers” thatperform despreading, Walsh decovering and accumulation, pilot time andfrequency tracking. Each finger outputs pilot and data symbols for thecorresponding path to digital signal processor (DSP) 140. DSP 140 thenperforms symbol demodulation and/or other signal processing.

[0029] As described above, although the Zero IF architecture eliminatesthe need for IF components, the architecture has typically requiredconventional devices to incorporate more complicated basebandcomponents. However, unlike a conventional digital VGA that mayimplement a relatively wide multiplier, digital VGA 132 operates in alogarithmic domain. In particular, digital VGA 132 scales digitalbaseband signal 129 within the logarithmic domain, and in accordancewith the logarithmic gain value 135 received from AGC 134. In thismanner, digital VGA 132 does not incorporate a complex and expensivemultiplier, but utilizes a more simple and relatively low cost adder. Inaddition, because digital VGA 132 operates in the logarithmic domain,the gain value 135 received from AGC 134 may be used without conversionto a linear value, thus removing the need for the conventional lookuptable (LUT) used for that purpose.

[0030] As discussed in further detail below, digital VGA 132 may utilizea logarithmic conversion unit (not shown in FIG. 1) to convert digitalbaseband signal 129 from a linear domain to a logarithmic domain, andmay utilize an exponential conversion unit (not shown) to convert ascaled baseband signal from the logarithmic domain back to the lineardomain. The exponential conversion unit and the logarithmic conversionunit may utilize lookup tables. Additional techniques described below,however, can be used to reduce the size of the lookup tables and thusreduce memory requirements. In other embodiments, the exponentialconversion unit and logarithmic conversion unit may utilize algorithms,possibly in combination with smaller sized lookup tables, to dynamicallygenerate the appropriate conversion values.

[0031]FIG. 2 is a flow diagram illustrating a high-level process inwhich digital VGA 132 (FIG. 1) scales a baseband signal in thelogarithmic domain. As shown, digital VGA 132 converts a linear basebandsignal from a linear domain to logarithmic domain (202). As described indetail below, digital VGA 132 may incorporate a logarithmic conversionunit that makes use of lookup tables to perform the conversion. Thelogarithmic domain may have units of decibels scaled to the desiredresolution so that conversion of the gain values can be avoided. Forexample, a resolution of {fraction (2/15)} dB may be used in a WCD,corresponding to the defined resolution of the gain.

[0032] Digital VGA 132 adds the baseband signal in the logarithmicdomain to gain values received from AGC 134, thereby generating a scaledbaseband signal in the logarithmic domain (204). The scaled basebandsignal may be, for example, amplified or attenuated depending on thegain values. Digital VGA 132 converts the scaled baseband signal backfrom the logarithmic domain to the linear domain (206). Digital VGA 132may incorporate an exponential conversion unit that makes use of lookuptables to perform the conversion. The scaled linear baseband signal canthen be processed, for example, by rake receivers 136 and digital signalprocessor 140 (208).

[0033]FIG. 3 is a block diagram illustrating an example embodiment ofdigital VGA 132 that operates within the logarithmic domain. As shown,digital VGA 132 includes a logarithmic conversion unit 302 that convertsan incoming linear baseband signal 129 into a logarithmic domain, suchas by converting the linear digital values to logarithmic values 305having units of decibels with a desired resolution. In one embodiment,logarithmic conversion unit 302 includes a logarithmic LUT that mapsacceptable values for linear baseband signals to the logarithmic values.Such a LUT, however, can require significant memory space. For thisreason, various additional techniques are described to reduce the sizeof the logarithmic LUT, and thereby reduce memory space requirements.

[0034] Digital VGA 132 includes an adder 306 rather than a conventionalmultiplier. In particular, digital VGA 132 exploits the logarithmicdomain, and replaces the multiplication function with addition. In otherwords, digital VGA 132 exploits the fact that Log(X*Y)=Log(X)+Log(Y), toeffectively replace a multiplier with adder 306. WCD 100, however, mayfurther process the amplified baseband signal in the linear domain.Therefore, digital VGA 132 may also include an exponential conversionunit 310 to convert the baseband signal back into the linear domainafter it has been scaled.

[0035] The gain of digital VGA 132 can be controlled by feedback fromAGC 134. In particular, AGC 134 may output a gain value 135 in thelogarithmic domain, such as in units of decibels having the desiredresolution. In this manner, digital VGA 132 need not convert the gainvalue 135 prior to application by adder 306. Rather, digital VGA 132 mayamplify or attenuate linear baseband signal 129 accordingly, simply byadding the gain value 135 to linear baseband signal 129 in thelogarithmic domain.

[0036] Exponential conversion unit 310 converts the scaled basebandsignal from the logarithmic domain back to the linear domain. Forexample, the exponential conversion unit 310 may use one or more LUTs,as described in greater detail below. In addition, the techniquesdescribed below may be used to significantly reduce the size of the oneor more exponential LUTs to reduce memory requirements.

[0037] In one particular case, digital VGA 132 operates in a logarithmicdomain having units of decibels scaled to a desired resolution. Asmentioned above, operating in a logarithmic domain having units ofdecibels can be particularly advantageous, because in that case the gainvalue generated by AGC 134 can be used without conversion. In otherembodiments, however, the invention may operate in other logarithmicdomains or non-linear domains. In still other embodiments, logarithmicconversion unit 302 and exponential conversion unit 310 implementalgorithms in addition to, or as an alternative to, the various LUTs.

[0038]FIG. 4 is a block diagram of one embodiment of digital VGA 132illustrated in greater detail. In particular, logarithmic conversionunit 302 is illustrated as including a logarithmic lookup table (LOGLUT) 402. In addition, logarithmic conversion unit 302 includes hardwarethat separates an incoming signed baseband signal into an unsignedabsolute value (ABS as shown at 406) and a sign bit (as shown at 410).In other words, the sign bit can be removed from the baseband signalwithin logarithmic conversion unit 302 and then propagated andreinserted in exponential conversion unit 310. The logarithm of anegative number is undefined. Thus, removing the sign bit from thebaseband signal avoids the scenario where hardware within the digitalVGA attempts to operate on negative numbers within the logarithmicdomain. Rather, specific hardware within digital VGA 132 may operateonly on positive numbers within the logarithmic domain once the sign bithas been removed.

[0039] In one particular example, A/D converter 128 (FIG. 1) producesthe digital baseband signal 129 as an 18-bit binary number, including asign bit, 7 integer bits, and 10 decimal bits. The sign bit is separatedfrom the baseband signal and the remaining 17-bit binary number,including 7 integer bits and 10 decimal bits, is fed into LOG LUT 402.As a result of the lookup, the 17-bit binary number is converted into a9-bit signed number, which is fed into adder 306. Adder 306 alsoreceives a 9-bit signed number from AGC 134 representing a gain value inunits of decibels with the desired resolution. Notably, the gain valueis already in the logarithmic domain, and thus requires no adjustmentprior to input into adder 306. Adder 306 adds the respective inputs toproduce a 10-bit result, which is fed into exponential conversion unit310. In one example, a relatively simple and low cost 9-bit adder isused.

[0040] Exponential conversion unit 310 may include saturation unit 424and at least one exponential LUT 428. The saturation unit can be used tosaturate the baseband signal in the logarithmic domain. For example,continuing with the example above, the 10-bit signed result, which isfed into exponential conversion unit 310, can be saturated to 7-bits bysaturation unit 424 to span a dynamic range represented by 128 possiblevalues. The output of saturation unit 424 is fed to exponential LUT 428along with the sign bit (as shown at 410) to generate a 4-bit signedresult representing the scaled baseband signal in the linear domain.Performing saturation prior to the lookup in exponential LUT 430 cansave memory space by reducing the required size of individual entries inexponential LUT 430. Moreover, truncation operations can be incorporatedinto exponential LUT 430. In other words, any conventional truncationoperations that would need to follow a conventional multiplier type ofVGA can be incorporated into exponential LUT 430 in accordance with theinvention simply by defining the appropriate bit-width of the output ofexponential LUT 430.

[0041]FIGS. 5A-5C illustrate three different exemplary embodiments of anexponential conversion unit according to the invention. The saturationunit 424 illustrated in FIG. 4 is not shown in FIGS. 5A-5C, but could beincluded for saturation prior to the lookups to reduce the size of oneor more LUTs within the exponential conversion unit. In addition,entries in the one or more LUTs within the exponential conversion unitmay have output bit-widths that effectively truncate digital inputsignals.

[0042] The exponential conversion unit 502 illustrated in FIG. 5A,includes different LUTs for positive and negative values. In particular,exponential conversion unit 502 includes EXP_LUT(pos) 506 that storesthe 128 possible positive 3-bit values, and also includes EXP_LUT(neg)510 that stores the 128 possible negative 4-bit values. The sign bit (asshown at 410) is used to provide input signal 514 used by multiplexer518 to select output from the appropriate LUT. Thus, when the sign bitidentifies a negative number, multiplexer 518 selects output fromEXP_LUT(neg) 510. When the sign bit identifies a positive number,multiplexer 518 selects output from EXP_LUT(pos) 506.

[0043]FIG. 5B illustrates yet another configuration of an exponentialconversion unit. In particular, exponential conversion unit 540, asillustrated in FIG. 5B, uses a single EXP_LUT(pos) 544 and replaces theEXP_LUT(neg) with an adder 548 that is used to generate thecomplimentary negative value from a positive value read fromEXP_LUT(pos) 544. For example, given a positive value X stored inEXP_LUT(pos), the complimentary negative value may be generated by theappropriate complimentary equation, in one case (−X−1). In other cases,however, where the negative and positive values are perfectly symmetricabout a Y-axis, the twos-complement equation of −X+1, or the like, maybe used to generate the negative values from the positive values.

[0044] Exponential conversion unit 540, as illustrated in FIG. 5B, canprovide advantages by further reducing memory requirements. Inparticular, exponential conversion unit 540 utilizes a single 128-bit by3-bit LUT, and adder 548. Exponential conversion unit 502 as illustratedin FIG. 5A, on the other hand, requires more memory space, buteliminates the additional adder. Each of the embodiments of FIGS. 5A and5B has advantages and disadvantages, which can be considered indetermining the best configuration for a given implementation.

[0045]FIG. 5C illustrates still another configuration of an exponentialconversion unit. Like the embodiment of FIG. 5B, exponential conversionunit 560 illustrated in FIG. 5C uses a single EXP_LUT(pos) 544. However,exponential conversion unit 560 generates negative values by invertingbits selected from EXP_LUT(pos) 544 and appending the sign bit. One'scomplement unit 568 can be used to perform the inversion and append unit574 can be used to append the sign bit after multiplexer 518 selects thedesired output. The embodiment of FIG. 5C avoids the need for anEXP_LUT(neg) as illustrated in FIG. 5A and also avoids the need for anadder as illustrated in FIG. 5B.

[0046]FIG. 6 is a block diagram, illustrating in greater detail, oneimplementation of logarithmic conversion unit 302. As mentioned above,logarithmic conversion unit 302 is used to convert digital values of asignal, e.g., an incoming linear baseband signal 129, into a logarithmicdomain. While logarithmic conversion unit 302 can be realized byimplementing a single LUT that maps acceptable values for linearbaseband signal to the logarithmic domain, an alternative configuration,as illustrated in FIG. 6, can significantly reduce memory requirements.

[0047] In particular, as illustrated in FIG. 6, logarithmic conversionunit 302 includes various hardware for manipulating a floating pointnumber. For example, an N-Bit positive binary number X(p) can beexpressed as X(p)=m*2^(E), where E is referred to as the exponent andrepresents the position of the most significant bit in X(p) that is setto a one, and m is referred to as the mantissa and represents theremaining E-1 least significant bits.

[0048] In a logarithmic domain having decibel units, the above floatingpoint equation can be expressed as:

20.log(X(p)/2¹⁰).R _(dB)=20.log(2^(E)/2¹⁰).R _(dB)+20.log(m).R _(dB,)

[0049] where R_(dB) is the inverse of the desired decibel resolution.The floating point equation in the logarithmic domain in decibel unitscan then be expressed as:

X=X _(E) +X _(m),

[0050] where X_(E) is the decibel value of the exponent and X_(m) is thedecibel value of the mantissa.

[0051] In this particular domain, X_(E) can be stored as a table of N=17entries, where each entry is 9-bits wide. Furthermore, X_(m) can bethought of as N segments. However, only one of the segments needs to bestored as a table, and values for all other segments can be derived fromentries of the stored segment. For example, the m^(th) segment includes2^(m-1) elements, each of which can be derived from an element of the(m+n)^(th) segment by left-shifting the input address of the (m+n)^(th)segment by n-bits. In addition, a nearest neighbor interpolation can beperformed to derive elements of the (m+n)^(th) segment from elements ofthe m^(th) segment. In particular, to interpolate an element of the(m+n)^(th) segment from an element of the m^(th) segment, the inputaddress of the m^(th) segment can be rounded by n-bits and used as theinput address of the (m+n)^(th) segment.

[0052] Referring again to FIG. 6, logarithmic conversion unit 302 mayinclude an exponent extractor 602 and a mantissa extractor 606. Anexponent LUT 612 can be used to generate the logarithmic value of theexponent. In addition, a mantissa LUT 616 can be used to generate thelogarithmic value of the mantissa. These values can then be combined byadder 620, and possibly truncated by truncate unit 624.

[0053] In one embodiment, mantissa LUT 616 maps all possible values ofthe various mantissa segments. However, to reduce the size of mantissaLUT 616 and thereby reduce memory requirements, address manipulationlogic 624 can be implemented to allow values of one segment of themantissa to be generated from a different segment of the mantissa. Inthis manner, only a single segment of the mantissa can be stored inmantissa LUT 616.

[0054] Address manipulation logic 624 may operate as follows. Assumingthat mantissa LUT 616 includes 2^(U) entries, then

if E>U, let input address M′=round(M/2^((E-U))), and

if E≦U, let M′=<<(U-E).

[0055] In other words, if E>U, then M′ is interpolated and defined asthe nearest neighbor input address in the stored mantissa LUT 616, andif E≦U. M′ is obtained by left shifting the input address by (U-E) bits.M′ can then be fed into the stored segment to yield the appropriateconverted value in the logarithmic domain.

[0056]FIGS. 7A and 7B are a series of two graphs that further illustratethe concept behind the embodiment of logarithmic conversion unit 302illustrated in FIG. 6. Again, the floating point equation in thelogarithmic domain having decibel units can be expressed asX=X_(E)+X_(m), where X_(E) is the decibel value of the exponent andX_(m) is the decibel value of the mantissa. FIG. 7A is a graph of thedecibel value of X as a function of linear input, in comparison to agraph of the decibel value of X_(E) for the same input. As can be seenin FIG. 7A, the value of X_(E) deviates slightly from the value of X atvarious different inputs.

[0057]FIG. 7B is a graph of the decibel value of X_(m). X_(m) can beviewed as the variation between X and X_(E) at the various differentinputs. Thus, as shown in FIG. 6, X can be generated from exponent LUT612 and mantissa LUT 616. In particular, exponential LUT 612 is used togenerate the logarithmic value of the exponent, and mantissa LUT 616 isused to generate the logarithmic value of the mantissa. Importantly,however, to save memory space, mantissa LUT 616 need only store entriesfor one of the spikes (i.e. segments) illustrated in FIG. 7A. The valuesof the other spikes can then be generated using address manipulationlogic 624 as described above.

[0058] The segment (or spike as illustrated in FIG. 7B) that is storedin mantissa LUT 616 can be chosen depending on the level of accuracyrequired. For example, the full logarithmic mantissa table can bederived without any loss by storing the last segment (in this case the17^(th) segment). However, that would result in the LUT having2¹⁷⁻¹=65,536 entries. Notably, because logarithmic functions tend toflatten at large inputs, a much smaller segment can be chosen without asignificant loss in performance in a wireless communication device. Inparticular, experiments have showed that storing the 7^(th) segmentyields acceptable approximations for all inputs. This would require amantissa LUT having only 2⁷⁻¹=64 entries.

[0059] Choosing a relatively small numbered segment for inclusion in themantissa table effectively results in non-uniform sampling over thelogarithmic function. At lower inputs, e.g., in lower segments, wherethe logarithmic function changes relatively rapidly, all values in lowernumbered segments can be generated from the larger numbered segment.However, at higher inputs, where the logarithmic function changes muchmore slowly, the values are interpolated from the stored segment. Thiscan be viewed as a sort of non-uniform sampling of the logarithmicfunction, wherein at lower inputs more data points are preserved, but athigher inputs, fewer data points are preserved. Experiments have shownthat such non-uniform sampling does not result in significantperformance reduction in a WCD.

[0060] To account for any unexpected variables, such as quantizationnoise, the resolution of both exponent LUT 612 and mantissa LUT 616 canbe increased by K-bits to help insure that the data is correct andnon-corrupted. Quantization noise may be introduced whenever a floatingpoint LOG function is represented by finite bit-width digital numbers.Experiments have showed that increasing the resolution of exponent LUT612 and mantissa LUT 616 by K=3 bits can be sufficient to compensate forquantization noise in a WCD.

[0061]FIG. 8 is a flow diagram illustrating a process that can be usedto reduce memory requirements when implementing one or more LUTs. Theprocess illustrated in FIG. 8 may be particularly effective when used ina WCD, but is not so limited. For example, the process of FIG. 8 may beused in any computer device implementing lookup tables.

[0062] As shown, a number is separated into an exponent component and amantissa component in a first domain (802). For example, the firstdomain may be a linear domain and the number may be binary floatingpoint number representing digital values of a signal. In that case, theexponent component can be extracted from the number simply byidentifying and storing the most significant bit that is set to one.Similarly, the mantissa component can be extracted from the numbersimply by storing the remaining least significant bits.

[0063] The exponent component can be converted from the first domain toa second domain, such as a non-linear domain (804). Separately, themantissa component can be converted from the first domain to the seconddomain (806). In one particular case, the second domain is a logarithmicdomain having units of decibels with the desired resolution. Onceconverted to the second domain (804 and 806), the exponent and mantissacomponents can be combined (808). For example, an adder can beimplemented to facilitate the combination simply by summing the exponentand mantissa components. If desired, the combination can then betruncated or rounded.

[0064] The conversion of the exponent component can be done using afirst LUT, e.g., an exponent LUT. Similarly, the conversion of themantissa component can be done using a second LUT, e.g., a mantissa LUT.Alternatively, either or both of the conversions may be achieved usingan algorithm, or an algorithm and a LUT in combination.

[0065] The exponent LUT may be relatively small, and may have entriescorresponding to the possible bit positions of the exponent. Forexample, if the number is a 17-bit number, the exponent LUT may haveonly 17 entries. The mantissa LUT, on the other hand, may include a muchlarger number of entries. For example, if the number is a 17-bit number,the mantissa LUT could include an extremely large number of entries. Forthis reason, additional techniques can be used to further reduce thesize of the mantissa LUT, and thus save memory space.

[0066]FIG. 9 is a flow diagram illustrating a process that can be usedto significantly reduce the size of the mantissa LUT. As shown, only asubset of a total number of mantissa values are stored in the mantissatable (902). Values not included in the subset can then be derived fromthe subset (904). In this manner, the memory requirements forimplementing a mantissa LUT can be reduced.

[0067] Referring again to FIG. 7B, the subset of mantissa values maycorrespond to one of the spikes illustrated in FIG. 7B. The values inall of the other spikes can be generated either by shifting the inputand selecting an entry in the subset based on the shifted input, or byinterpolating input and selecting an entry in the subset based on theinterpolated input. If a value in a smaller numbered mantissa segment isneeded (i.e., a segment located to the left of the stored segment inFIG. 7B), the shifting operation can be used. If a value in a largernumber mantissa segment is needed (i.e., a segment located to the rightof the stored segment in FIG. 7B), the interpolation operation can beused. In this manner, the total number of possible mantissa values canbe generated, as needed, from a much smaller subset of mantissa entriesstored in a table, thus saving memory space.

[0068] In particular, if a value in a larger number mantissa segment isneeded, the input address of that value is interpolated and defined asthe nearest neighbor input address within the stored mantissa segment.If a value in a smaller numbered mantissa segment is needed, the inputaddress of that value is left shifting by a number of bits correspondingto the difference between the number of the stored segment and thenumber of the segment for the desired value. The interpolated address orshifted address can then be fed into the stored segment to yield theappropriate converted value.

[0069] As mentioned above, the particular subset is stored in themantissa LUT can be chosen depending on the level of accuracy required.Notably, because logarithmic functions tend to flatten at large inputs,a small segment can be used without a significant loss in performance ina wireless communication device. In particular, experiments showed thatstoring the 7^(th) segment yielded acceptable approximations for allinputs. This would require a mantissa LUT having only 2⁷⁻¹=64 entries.

[0070] In still other embodiments, a somewhat larger mantissa LUT,including entries that comprise non-uniform sampling of the logarithmicor logarithmic like functions can be used. For example, the entriescould be pre-computed using the techniques described above. In otherwords, a segment of the mantissa could be selected and all of the valuesin smaller segments could be pre-computed and included within the LUT.However, for larger segments, the entries could be pre-computedaccording to the interpolation technique described above. In thismanner, every segment stored within the LUT would have no more entriesthan the chosen segment, thus limiting the amount of required memoryspace. Although the mantissa LUT would be larger than a LUT storing onlythe single segment, the address manipulation logic would not be needed.In designing a particular implementation, the additional memory spacerequired can be weighed against the inclusion of address manipulationlogic to determine the best, or most efficient configuration.

[0071] The various LUTs described above may be stored in memory andaccessed as needed. In some cases, methods described above may beimplemented in software, such as program code. For example, the programcode can be loaded into memory and then executed in a processor. Theprogram code can be initially carried on computer-readable media such asa hard drive or magnetic, optical, magneto-optic, phase-change, or otherdisk or tape media. Alternatively, the program code may be loaded intomemory from electronic computer-readable media such as EEPROM, ordownloaded over a network connection. If downloaded, the program codemay be initially embedded in a carrier wave or otherwise transmitted onan electromagnetic signal. The program code may be embodied as a featurein an application program providing a wide range of functionality.

[0072] If the invention is implemented in program code, the processorthat executes the program code may take the form of a microprocessor andcan be integrated with or form part of a PC, Macintosh, computerworkstation, hand-held data terminal, palm computer, WCD, wireless basestation, network router, or the like. The memory may include randomaccess memory (RAM) storing program code that is accessed and executedby processor to carry out the various method described above.

[0073] Various embodiments of the invention have been described. Forexample, a digital VGA has been described for use in a WCD. Inparticular, the digital VGA operates within the logarithmic domain, andreplaces a conventional multiplier and a conventional exponential lookuptable having a size greater than 1000 bytes, with an adder, logarithmicLUTs of nominal size (i.e. approximately 200 bytes of total space) and asmaller exponential table of nominal size (i.e. approximately 128bytes). Nevertheless, various modifications may be made withoutdeparting from the spirit and scope of the invention. For example,rather than implementing lookup tables, the invention could be realizedusing algorithms that dynamically convert from logarithmic domains tolinear domains, and/or vice versa. In addition, the invention could beimplemented in other logarithmic domains. Moreover, the digital VGAaccording to the invention could be used in other devices, including,for example, a base station within a wireless communication network. Forexample, any device that implements a multiplier followed by some sortof truncation may benefit from the invention.

[0074] In addition, aspects of the invention could be used inapplications other than digital VGA's. For example, any apparatus thatperforms a multiplication operation followed by a truncation operationcould use aspects of the invention to replace a conventional multiplierwith an adder. In one case, the invention can be implemented to multiplytwo baseband signals using an adder rather than a multiplier. Ingeneral, the invention can perform multiplication and truncation byconverting linear digital values to a logarithmic domain, adding thedigital values in the logarithmic domain and then converting the addedvalue back to a linear domain. Moreover, a truncation operation can beincorporated into a lookup table that is used to convert back to thelinear domain simply by choosing output bit-widths to effectivelytruncate the signals.

[0075] Various techniques for reducing the size of LUTs so as to reducememory requirements have also been described. In particular, many ofthese techniques have been described in the context of a WCD. However,the invention is not limited in that respect. For example, thetechniques used to reduce the size of one or more LUTs could also beused in other computer devices to save memory space. Accordingly, theseand other embodiments are within the scope of the following claims.

1. A method comprising: converting a first digital signal from a lineardomain to a logarithmic domain, adding the converted digital signal anda second digital signal to generate a scaled digital signal; andconverting the scaled digital signal from the logarithmic domain to thelinear domain.
 2. The method of claim 1, wherein the first digitalsignal is a baseband signal and the second digital signal is a gainvalue.
 3. The method of claim 1, wherein the first digital signal is afirst baseband signal and the second digital signal is a second basebandsignal, the method further comprising converting the second digitalsignal from a linear domain to a logarithmic domain prior to adding theconverted digital signal and the second digital signal.
 4. The method ofclaim 1, further comprising processing the scaled digital signal in thelinear domain.
 5. The method of claim 1, further comprising convertingthe first digital signal from the linear domain to the logarithmicdomain by accessing a lookup table.
 6. The method of claim 1, furthercomprising converting the scaled digital signal from the logarithmicdomain to the linear domain by accessing a lookup table.
 7. The methodof claim 1, further comprising saturating the scaled digital signalprior to converting the scaled digital signal from the logarithmicdomain to the linear domain.
 8. The method of claim 1, furthercomprising truncating the scaled digital signal prior to converting thescaled digital signal from the logarithmic domain to the linear domain.9. The method of claim 2, wherein the scaled digital signal is anattenuated signal having a value less than the baseband signal.
 10. Themethod of claim 2, wherein the scaled digital signal is an amplifiedsignal having a value greater than the baseband signal.
 11. A methodcomprising: converting a baseband signal from a linear domain to alogarithmic domain; adding the converted baseband signal to a gain togenerate a scaled baseband signal; saturating the scaled basebandsignal; converting the saturated baseband signal from the logarithmicdomain to the linear domain; and processing the saturated basebandsignal in the linear domain.